Curriculum Vitae

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PhD Electrical and Computer Engineering, Rice University, 1989.
MS Electrical and Computer Engineering, Rice University, 1985.
BS Electrical Engineering (with honors), Texas Tech University, 1973.

Employment and Professional Experience:
08/11 – present: Technical Consultant
04/09 – present: The University of Texas at Dallas
05/79 – 03/09: Texas Instruments Incorporated
08/73 – 03/79: U.S. Air Force

Experience (Summary):
• Twenty-five years MOS circuit design experience emphasizing transistor-level circuit design of MOS circuits (analog, digital, mixed-signal, system interface), integrated circuit architecture, memory-related circuits and architectures (EPROM, Flash Memory, DRAM, and SRAM), memory interfaces and interface circuits, SPICE simulation, layout, parasitic extraction, full-chip simulation including power bus and interconnect parasitics, DRC, LVS, chip architectures, and design methodology.
• Extensive experience interacting with process development and process integration teams including:
  – Knowledge of EPROM, Flash, DRAM, and SRAM memory technologies and storage cell structures.
  – Knowledge of analog and digital CMOS process technologies, device structures, design rules, and design/process interaction.
  – Knowledge of semiconductor devices and device physics from the design perspective.
  – Experience in use of TCAD simulators (SUPREM3, TSUPREM4, Medici) and statistical design tools.
• Patent committee member (MOS Memory Division, 8 years) responsible for evaluating submitted disclosures for significant value based on novelty and enforceability, reading and understanding claims, analyzing if products infringe claims, researching potential prior art, evaluating issued patents for patent incentive awards based on internal and external use.
• Five years design management experience leading design teams from 5 to 22 people.
• Three-plus years experience managing a product engineering team specializing in test, redundancy repair, debug, and yield analysis of embedded cache SRAMs for SPARC microprocessors.

Assignment Details (Technical Consultant):
08/11 – Present: Technical Consultant
• Integrated circuit contract design.
• Patent and intellectual property consultant.

Assignment Details (University of Texas at Dallas):
04/09 – Present: Research Scientist (04/09 – 12/11), Visiting Researcher (12/11 – present), Dept. of Materials Science and Engineering
• Development of devices and circuits utilizing organic and inorganic semiconductors for flexible electronics.
• Development of bio-molecular sensor devices for medical applications, sensor device SPICE models, and sensor support circuits.
• Research into low-temperature fabrication of neuromorphic circuits and associated SPICE modeling.
• Research in analog circuits and floating gate devices.

Assignment Details (Texas Instruments):
12/05 – 03/09: Senior Member, Technical Staff, Analog Technology Development Group
• Senior design engineer and technical contributor for a team responsible for developing memory technologies, including non-volatile memory (Flash Memory, EEPROM, OTP) and static RAMs, for Analog and Mixed Signal Technologies.

11/04 – 12/05: Senior Member, Technical Staff, RFID Business UHF Engineering Group
• Responsible for working with Technology Development to define the roadmap for RFID next-generation Non-Volatile Memory (NVM). Work with Technology Development and External Manufacturing to define SC technology roadmap for RFID. Enable and staff IC design team for RFID UHF Engineering Group and put design tools in place. Define technology and simulation methodology to enhance RFID. Participate in debug and analysis of prototype devices as needed.

12/00 – 11/04: Manager, SRAM Test Engineering, SPARC Products Group
• Responsible for managing a group of test engineers that provide embedded SRAM test programs, redundancy analysis, and laser/eFuse repair for all new Sun SPARC microprocessors. Supported test, design debug, failure analysis, and yield improvement of microprocessor cache SRAMs.

2/99 – 12/00: SMTS and Design Engineer, Mixed Signal Products
• Senior design engineer responsible for circuit design and supervision of layout for various circuit components for mixed-signal integrated circuits.

1/96 – 1/99: SMTS and Senior Design Engineer
• Conducted evaluations of statistical modeling and circuit design tools. Initiated the first effort within TI to pursue statistical SPICE model generation and circuit simulation. This effort was subsequently transferred to the SPICE model labs and the MSLP statistical design group.
• Responsible for evaluation of potential product opportunities utilizing Merged DRAM and Logic technology. Conducted architecture studies and cost analysis of product opportunities.
• Senior design engineering member of System Interface Team supporting analysis and debug of system-related product issues.
• Responsible for resolving all customer-related design issues with the PTEC Custom Flash Lifetime Buy after the sale of the MOS Memory Division to Micron.

1990 – 1995: Project Design Manager, Flash Memory
• Managed the design of the 28F010, 28F210, and 28F512 flash memories. These 1Mbit and 512Kbit devices were the first TI high-volume production flash memory products.
• Tasks included working with Process Development and Technology groups to develop process requirements and a production-worthy Flash technology and solve technology issues such as over-erase and program/erase endurance.
• Managed the design of the PTEC custom flash memory product for Ford. Supervised a large design team which completed a very complex design on schedule to customer requirement. The PTEC project achieved first-pass design success and on time delivery of samples which met Ford’s critical milestones when the second-source competitor failed, resulting in TI being awarded 100% of the business.
• Principal developer of procedural design methodology for Commodity Flash Memory products and subsequent derivatives.

1989 – 1990: Senior Design Engineer, Flash Memory
• Senior technical contributor to the design of development vehicles for 5V-only Flash Memory technology.

6/85 – 1989: Senior DRAM Design Engineer
• Principal contributor to architectural analysis and circuit design of the initial version of the 16Mbit DRAM.
• Key contributor in working with Process Development / Process Integration engineers to define the storage cell, design rules, and process requirements.
• Responsible for multiple design debug and productization tasks on the 1Mbit DRAM generation and support of 4Mbit DRAM productization. Performed full-chip SPICE simulation, including simulation of power bus structure and interconnect parasitics for major global signals, and chip-level LVS.

9/83 – 5/85: On Educational Leave of Absence at Rice University.

5/79 – 8/83: Design Engineer
• Design engineer on 16K thru 128K EPROMS.
• Responsible for all circuit design, SPICE simulation, layout, and LVS of complete designs, as well as some test and laboratory debug of prototypes.
• Contributing design engineer on 64K and 1Mbit DRAM generations.

U. S. Patents:
• 15/173,217 (Filed), Patel, Ujas N., Marshall, Andrew, Stiegler, Harvey J. and Jarreau, Keith M. “Mismatch Correction in Differential Amplifiers Using Analog Floating Gate Transistors.”
• 9,042,173, Stiegler, Harvey J. and Dang, Luan, “Efficient Memory Sense Architecture.”
• 8,908,412, Stiegler, Harvey J. and Mitchell, Allan T., “Array Architecture for Reduced Voltage, Low Power, Single Poly EEPROM.”
• 8,174,884, Mitchell, Allan T. and Stiegler, Harvey J., “Low Power, Single Poly EEPROM Cell with Voltage Divider.”
• 5,786,702, Stiegler, Harvey J. and Krzentz, Steven V., “Method for detecting defects in integrated-circuit arrays.”
• 5,773,997, Stiegler, Harvey J., “Reference circuit for sense amplifier.”
• 5,528,543, Stiegler, Harvey J., “Sense amplifier circuitry.”
• 5,313,432, Lin, Sung-Wei, Schreck, John F., Truong, Phat. C., McElroy, David J., Stiegler, Harvey J., Ashmore, Jr., Benjamin H., Gill, Manzur, “Segmented, multiple-decoder memory array and method for programming a memory array.”
• 4,692,638, Stiegler, Harvey J., “CMOS/NMOS decoder and high-level driver circuit.”

Honors and Awards:
Senior Member, Technical Staff, Texas Instruments, elected 1993 Member, Group Technical Staff, Texas Instruments, elected 1990 NSF Graduate Student Fellowship

Professional Memberships and Technical Activities:
• Life Senior Member, IEEE, IEEE Computer Society, and IEEE Electron Devices Society
• Member, American Physical Society
• Member, American Association for the Advancement of Science
• Member, Tau Beta Pi, Engineering Honorary
• Member, Eta Kappa Nu, Electrical Engineering Honorary

Additional Past Technical Activities:
• Industry mentor to the IRAM (Intelligent RAM) project, University of California Berkeley.
• Member, Corporate Patent Committee, Texas Instruments
• Member, MOS Memory Division Patent Committee, Texas Instruments
• IDEA Program Representative, Texas Instruments
• Member, Design Methodology QIT, MOS Memory Division, Texas Instruments
• Member, SPICE Model Council, Texas Instruments

Additional Interests and Activities:
• Member of the Board of Directors, Vice President,and President, Voices of Change – New Music Ensemble of Dallas, 2009-2015
• Member of the Board of Directors, Dallas Symphony Orchestra Guild, 2012-2014.
• Member of the Board of Directors and President, Open Classical, 2014-present.